GanoSIC — GaAs-on-SiC Vertical Power Module · bareket.ai

AI data centers lose
10% of power
in the last inch.

BareketAI moves power conversion from beside the processor to directly underneath it — delivering 1,000 amps through 1.5mm of PCB at 98% efficiency.

0%
power efficiency
at peak load
0A
continuous current
delivery
0%
resistance vs
lateral delivery
0°C
internal silicon
temperature Tj
The problem we solve

The last-inch power crisis

As AI GPUs cross 4kW, the horizontal copper path between the voltage regulator and the processor becomes the system-level bottleneck. BareketAI eliminates it.

Today — lateral delivery
Power travels inches sideways to reach the GPU
Voltage regulators sit beside the processor. Current flows through long horizontal copper traces — resistive, lossy, prone to droop. At 1,000 amps, every millimeter of copper wastes power.
GanoSIC — vertical delivery
Power travels 1.5mm straight up through the PCB
The GanoSIC module mounts directly beneath the GPU die. Current path collapses from inches to 1.5mm — 90% lower resistance, 98% efficiency, zero voltage droop at 1,000 amps continuous.
All-Israel supply chain

Built in Israel, end to end

Three world-class Israeli institutions. One continuous fabrication chain. No dependence on foreign foundries for the core device.

01
GAL-EL (MMIC)
Wafer fabrication · Ashdod
02
TAU Nano Center
Die bonding · characterization
03
PCB Technologies
12-layer HDI · EVB build
04
GanoSIC EVB
1,000A · 98% efficiency demo
GanoSIC architecture

The vertical power module

GaAs-on-SiC combines the electron mobility of gallium arsenide with the thermal conductivity of silicon carbide — a material pairing purpose-built for high-current vertical power delivery beneath the GPU die.

PCB stack-up
Supply chain flow
Thermal architecture
L1–L4
Signal routing
PCIe Gen 6/7 · 1.6T differential pairs · 85Ω controlled impedance
L5–L8
Power planes
Ultra-thick 4oz copper · 1,000A routing · GND return planes
L9–L12
GanoSIC zone
Thermal via array · die mount · dual-sided cooling interface
Step 01
GAL-EL
Wafer fab · Ashdod
Step 02
TAU Nano
Die bonding · Tel Aviv
Step 03
PCB Tech
HDI board · Israel
Step 04
GanoSIC EVB
1,000A · 98% eff.
GAL-EL fabricates GaAs-on-SiC epitaxial wafers — 10 to 25 wafer R&D lot. Wafer-level electrical testing (DC IV, breakdown voltage) before delivery.
Primary cold plate
Top-side liquid cooling · conventional
GPU die (4kW)
AI GPU silicon — the heat source
Package substrate
Conventional interface layer
GanoSIC VPM
Bottom-side extraction · 420 W/m·K SiC
PCB layers L9–L12
Thermal via array · heat escape path
420 W/m·K
SiC thermal conductivity
Silicon Carbide conducts heat nearly as efficiently as pure copper — extracting heat vertically through the module bottom-side.
−20°C
Junction temperature reduction
15–20°C reduction in internal silicon Tj, enabling higher sustained GPU clock speeds without thermal throttling.
Dual path
Two-sided cooling
Top cold plate + GanoSIC bottom extraction simultaneously — reaching hotspots that single-sided cooling cannot access.
Technical specifications

GanoSIC V1 performance targets

Device architectureGaAs active layer on SiC substrate (heterojunction)
Thermal conductivity420 W/m·K — SiC substrate
Switching frequency10× silicon — GaAs electron mobility advantage
Current density>1,000 A/cm² vertical conduction
Output voltage0.8 – 1.0V stable at 1,000A full load
Power efficiency98% at peak load
Current path1.5mm vertical vs. inches lateral (−90% resistance)
EVB footprint100mm × 100mm evaluation board
CTE — GaAs / SiC6.1 / 4.0 ppm/K — managed by AuSn die attach process
Wafer lot size (PoC)10 – 25 wafers — R&D run at GAL-EL, Ashdod
12-month development program

From concept to working hardware

Phase 1 · Months 0–3 · Active now
Architecture definition
GAL-EL process feasibility review. TAU Nano Center capability assessment. NDA execution with all partners. Epitaxial stack design consultation. PCB Technologies architecture kick-off.
Phase 2 · Months 3–8
Prototype development
GAL-EL GaAs-on-SiC wafer fabrication — 10–25 wafer R&D lot. TAU wire bonding and AuSn die attach. SEM/TEM inspection post-assembly. PCB Technologies 12-layer HDI layout and prototype build.
Phase 3 · Months 8–12
Demonstration hardware
EVB build and full assembly. 1,000A current delivery test. 98% efficiency demonstration at peak load. Thermal validation — −15°C Tj confirmed. Full performance verification report. Seed raise begins.
Target markets

Four verticals. One architecture.

GanoSIC is designed for multi-market deployment from day one — the same vertical power architecture addresses AI infrastructure, automotive electrification, defense electronics, and RF power systems.

AI data centers
As AI GPU cards cross 4kW, conventional lateral power delivery becomes the system bottleneck. GanoSIC eliminates the last-inch resistance loss — enabling denser GPU clusters, higher sustained clocks, and measurably lower power costs at hyperscale.
Primary long-term market · 4kW GPU class · hyperscaler power density
Automotive electrification
DC/DC converters and onboard chargers in EVs demand compact, high-efficiency power conversion that operates reliably across extreme temperature ranges. GanoSIC's SiC substrate and vertical architecture delivers superior thermal performance for 400V and 800V EV platforms — targeting AEC-Q101 qualification. Named customers include ABB E-mobility and Electreon.
18–36 month revenue bridge · DC/DC converters · OBC · AEC-Q101 · ABB E-mobility · Electreon
Defense electronics
Defense platform power subsystems demand compact, high-efficiency power conversion that conventional silicon cannot deliver. GanoSIC addresses airborne and naval radar RF power, electronic warfare systems, and ruggedized field-deployed AI inference platforms — with a fully sovereign supply chain. Named customer: Elbit Systems.
Fastest path to first revenue · 12–18 months · IDF platforms · EW · Elbit Systems
RF power systems
GaAs electron mobility enables switching frequencies 10× higher than silicon — directly applicable to high-power RF amplifiers, phased-array radar drivers, and microwave power modules where frequency and efficiency co-determine system performance.
GaAs MMIC-adjacent · radar · EW power stages · co-packaged optics
Strategic importance

An all-Israel defense supply chain

A GanoSIC device fabricated at GAL-EL, packaged at TAU Nano Center, and integrated on a PCB Technologies board is a complete Israeli-sourced compound semiconductor power module — no dependence on foreign foundries for the core device.

Strategic note — Shimon Eidelman, Chairman & CEO · BareketAI
"This is strategically significant for defense procurement and ITAR compliance. An Israeli-designed, Israeli-fabricated, Israeli-packaged power semiconductor device — for the first time."
BareketAI · bareket.ai · 2026
Partner matrix

Three institutions. One mission.

Each partner was chosen for a specific and irreplaceable capability. Together they form Israel's first complete GaAs-on-SiC semiconductor supply chain — from raw epitaxial wafer to working evaluation board.

Partner 01
Wafer fabrication
GAL-EL (MMIC)
Ashdod, Israel
Israel's only compound semiconductor foundry with decades of GaAs III-V process expertise. GAL-EL fabricates the GaAs-on-SiC epitaxial wafers that form the physical foundation of every GanoSIC device — the most upstream and critical stage of the program.
GaAs epitaxyMOCVD / MBEIII-V processWafer-level testDefense-adjacent
Partner 02
Die bonding + characterization
TAU Nano Center
Tel Aviv University, Israel
The Jan Koum Center for Nanoscience & Nanotechnology at Tel Aviv University provides precision die bonding, wire bonding, and analytical characterization. TAU develops and validates the GanoSIC bonding process to BareketAI's specification — with a path to IIA joint R&D funding.
Wire bondingAuSn die attachSEM / TEMFIB / EDXThermal imaging
Partner 03
PCB design + evaluation board
PCB Technologies
Israel
Israel's leading HDI PCB house, with a dedicated iNPACK division capable of production-scale wire bonding, die attach, and bump processing on 8" wafers. PCB Technologies builds the 12-layer HDI evaluation board that demonstrates 98% efficiency at 1,000 amps — at IAI and Elbit quality tier.
12-layer HDIUltra-thick CuiNPACK bondingIAI / Elbit tierEVB build
Supply chain flow

From epitaxial wafer to working hardware

01 · GAL-EL
Wafer fabrication
10–25 wafer R&D lot
02 · TAU Nano
Die bonding
AuSn · SEM/TEM validation
03 · PCB Tech
PCB + EVB build
12-layer HDI assembly
04 · GanoSIC
Performance demo
1,000A · 98% efficiency
About BareketAI
SE
Shimon Eidelman
Founder & CEO · BareketAI
EGMO · Amdocs · BSG

The founder thesis

The GPU power delivery problem is not a software problem, not an architecture problem, and not a cooling problem. It is a geometry problem — and it has a physical solution. When you move the voltage regulator from beside the chip to directly beneath it, the laws of physics do the rest.

Why GaAs-on-SiC

Silicon power devices are approaching their material limits. GaN improved on silicon, but it inherits silicon's thermal constraints in vertical architectures. GaAs-on-SiC is the only material combination that simultaneously delivers the electron mobility needed for high-frequency switching and the thermal conductivity needed for vertical heat extraction in a 4kW GPU environment.

Why Israel

Israel has GAL-EL — the only compound semiconductor foundry in the country with decades of GaAs III-V expertise. It has TAU's world-class Nano Center. It has PCB Technologies, which builds HDI PCBs for IAI and Elbit. The complete supply chain already exists. GanoSIC is the product that connects it.

Pre-Seed · $4M · now Seed · $20–30M · months 6–10 Series A · scale
The team

World-class execution. Insider access to every key partner.

SE
Shimon Eidelman
Founder & CEO
EGMOAmdocsBSG
20+ years leading semiconductor & telecom infrastructure projects across Israel and Europe. FAB construction, systems integration, and turnkey delivery.
JK
Joseph Kaplun
CTO / VP R&D
GAL-ELNano-DimensionsIAI ELTA
PhD. Former CTO of GAL-EL — Bareket's foundry partner. Deep expertise in compound semiconductor process development, 3D printing, and high-yield fab operations.
MS
Max Shrager
COO
iNPACKPhononicsTechnion
M.Sc. Applied Statistics. 20+ years in advanced manufacturing, additive electronics, and PCB production. Former iNPACK — Bareket's production bonding partner.
SM
Dr. Shaul Michaelson
Senior Scientist
Tower SemiTechnionPhononics
15+ years at Tower Semiconductor in R&D process engineering. Materials science expert — diamond, SiC, advanced characterization. Technion lab engineer.
Board advisors

Deep industry expertise. Strategic guidance at every stage.

AH
Adam Hofmann
Mentor & Board Advisor
PhononicsGanoSIC Co-Inventor
Co-inventor of the core GanoSIC patent. Deep expertise in GaAs-on-SiC compound semiconductor processes. Mentor to BareketAI from inception — his know-how is embedded in every layer of GanoSIC architecture.
RE
Roni Elshikh
Board Advisor
AWZ VenturesDefense & Deep Tech
Senior executive with deep expertise in semiconductor investment and defense electronics. AWZ Ventures — strategic investor in deep tech and advanced hardware platforms.
MW
Mike Weizman
Board Advisor
Strategic AdvisorFundraising
Strategic collaborator supporting BareketAI's fundraising and business development. Deep network across venture capital and deep tech investment communities.
Get in touch

Let's build the future of AI power infrastructure together

Whether you're a potential investor, technology partner, or institution interested in GanoSIC — we respond to all serious inquiries within 48 hours.

Full die specification shared only after NDA execution.

Investor
Pre-Seed round active · Seed raise months 6–10 · strategic + financial
Technology partner
Foundry · packaging · PCB · characterization labs
Defense & government
IDF procurement · defense R&D · dual-use applications
Press & media
Technology coverage · investor announcements · milestones
Full technical specification — including die architecture, epitaxial stack, and process parameters — is shared exclusively following NDA execution. This form initiates that process.